Block Diagram Of The Low Power Consumption Control Circuit - Fujitsu MB90460 Series Hardware Manual

CHAPTER 6 LOW POWER CONSUMPTION MODE
6.2 Block Diagram of the Low Power Consumption Control
Circuit
The low power consumption control circuit consists of the following seven blocks:
• CPU intermittent operation selector
• Standby clock control circuit
• CPU clock control circuit
• Peripheral clock control circuit
• Pin high-impedance control circuit
• Internal reset generation circuit
• Low power consumption mode control register (LPMCR)

■ Block Diagram of the Low Power Consumption Control Circuit

Figure 6.2-1 shows the block diagram of the low power consumption control circuit.
Figure 6.2-1 Block diagram of the low power consumption control circuit
Pin
RSTX
Release reset
Cancel interrupt
Clock generator
Pin
X0
X1 Pin
92
Low power mode control register (LPMCR)
STP SLP SPL RST TMD
CPU intermittent
operation selecter
3
Clock selector
x1 x2 x3 x4
PLL multipiler
RESV MCM
circuit
Clock selection register (CKSCR)
Divide-
by-2
Main clock
System clock
generation circuit
CG1 CG0 RESV
Pin high
impedance
control circuit
Internal reset
generation
circuit
CPU clock
control circuit
RST
Standby control
circuit
Machine clock
Peripheral clock
control circuit
Oscillation stabiliz-
-ation wait is passed
2
2
WS1 WS0 RESV MCS CS1
Divide- Divide-
Divide-
by-512 by-2 by-4
Pin Hi-z control
Internal reset
Select intermittent cycles
CPU clock
Stop and sleep signals
Stop signal
Peripheral clock
Oscillation stabilization
wait interval selector
CS0
Divide- Divide-
by-4
by-4
Time-base timer