Fujitsu MB90460 Series Hardware Manual page 387

CHAPTER 15 MULTI-PULSE GENERATOR
■ Block Diagram of Multi-pulse Generator Pins
Port data direction register (DDR)
Figure 15.3-2 Block Diagram of P12/INT2/DTTI1 to P15/INT5/TIN0 Pins
RDR
Port data register (PDR)
PDR read
PDR write
Port data direction register (DDR)
DDR write
DDR read
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Figure 15.3-1 Block Diagram of P00/OPT0 to P05/OPT5 Pins
RDR
Port data register (PDR)
PDR read
Output latch
PDR write
Direction latch
DDR write
DDR read
Output latch
Direction latch
Figure 15.3-3 Block diagram of P43/SNI0 to P45/SNI2 pins
Port data register (PDR)
PDR read
Output latch
PDR write
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Resource output Direct resource input
Resource output enable
Standby control (SPL = 1)
Resource output Resource input
Resource output enable
Standby control (SPL = 1)
Resource output
Resource output enable
Standby control (SPL = 1)
Pull-up resistor
About 50kΩ
Pin
Pull-up resistor
About 50kΩ
Pin
Resource input
Pin