Fujitsu MB90460 Series Hardware Manual page 244

Figure 11.4-2 Clear Timing and Watchdog Timer Intervals
[WDG timer block diagram]
Clock
selector
WTE bit
[Minimum interval] When the WTE bit is cleared immediately before the count clock rises:
Counter clearing
Count clock a
Divide-by-two
value b
Divide-by-two
value c
Count enabling
Reset signal d
WTE bit clearing
[Maximum interval] When the WTE bit is cleared immediately after the count clock rises:
Counter clearing
Count clock a
Divide-by-two
value b
Divide-by-two
value c
Count enabling
Reset signal d
WTE bit clearing
2-bit counter
Divide-by- Divide-by-
two circuit two circuit
Count enabling and clearing
Count enable
output circuit
Count start
7 x (count clock cycle/2)
Count start
9 x (count clock cycle/2)
CHAPTER 11 WATCHDOG TIMER
Reset
Reset signal
circuit
Watchdog reset generation
Watchdog reset generation
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