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CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Making Non-overlap Signals by using RT1/RT3/RT5 in Inverted Polarity
(DTCR0/DTCR1/DTCR2:TMD2 to TMD0=100
When selecting non-overlap signal for a active level "1" (inverted polarity) in DTCR0/DTCR1/
DTCR2:DMOD, a delay corresponding to the non-overlap time set in the TMRR0/TMRR1/TMRR2
register (16-bit timer register) is applied. The delay is applied at a rising edge of RT1/RT3/RT5 or its
falling edge. If RT1/RT3/RT5 pulse width is smaller than the set non-overlap time, the 16-bit timer will
restart down-counting from TMRR0/TMRR1/TMRR2 value at the next RT's edge.
Figure 14.6-26 Non-overlap Signal Generation by RT1/RT3/RT5 in Inverted Polarity
Setting up registers:
• TCDT
• TCCS
• OCCP0 to OCCP5: XXXX
• TMRR0 to MRR2 : XXXX
• SIGCR
Note:
"X" must be set according to the operation.
16-bit timer 0
Count
value
RT1
RTO0 (U)
RTO1 (X)
344
: 0000
H
: XXXXXXXXXX0X0XXX
(Compare value)
H
(Non-overlap timing setting)
H
: XXXXXXXX
(DTTI0 input and 16-bit timer count clock setting)
B
1 machine cycle
Pin name
RTO0 (U)
Inverted signal with delay is applied at RT1 rising edge
RTO2 (V)
Inverted signal with delay is applied at RT3 rising edge
RTO4 (W)
Inverted signal with delay is applied at RT5 rising edge
RTO1 (X)
Signal with delay is applied at RT1 falling edge
RTO3 (Y)
Signal with delay is applied at RT3 falling edge
RTO5 (Z)
Signal with delay is applied at RT5 falling edge
)
B
• CPCLR
• OCS0 to OCS5
B
• DTCR0 to DTCR2 : 1XXXX100
1.5 machine cycle
Output signal
: XXXX
(Cycle setting)
H
: -XX1XXXXXXXXXX11
B
B
TMRR0 set value
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