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■ TImer Control Ctatus Register, Lower Byte (TCCSL)
Address bit7
00005E
BFE STOP MODE SCLR CLK2 CLK1 CLK0 -0100000
H
R/W
R/W
R/W : Read and write
: Initial value
—
: Not used
Figure 14.4-9 Timer Control Status Register (TCCSL)
6
5
4
3
R/W
R/W
R/W
CLK2 CLK1 CLK0
0
0
0
0
1
1
1
1
φ: Machine cycle
SCLR
0
1
MODE
0
1
STOP
0
1
BFE
CHAPTER 14 MULTI-FUNCTIONAL TIMER
2
1
0
Initial value
R/W
R/W
R/W
Count
clock
φ
0
0
φ/2
0
1
φ/4
1
0
φ/8
1
1
φ/16
0
0
φ/32
0
1
φ/64
1
0
φ/128
1
1
Write
Clear SCLR bit
Initialize counter to "0000
Timer counting mode
Counting is enabled (operation)
Counting is disabled (stop)
Compare clear buffer enable bit
0
Disable compare clear buffer
1
Enable compare clear buffer
B
Clock frequency selection bit
φ = 16 MHz
φ = 8 MHz
φ = 4 MHz
0.25 µs
62.5 ns
125 ns
0.25 µs
0.5 µs
125 ns
0.25 µs
0.5 µs
1 µs
0.5 µs
1 µs
2 µs
1 µs
2 µs
4 µs
2 µs
4 µs
8 µs
4 µs
8 µs
16 µs
8 µs
16 µs
32 µs
Timer clear bit
Read
Always read as "0"
"
H
up-count mode
up-down count mode
Timer enable bit
φ = 1 MHz
1 µs
2 µs
4 µs
8 µs
16 µs
32 µs
64 µs
128 µs
297
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