Timer Control Status Register (Tmcsr); Figure 15.3.1A Timer Control Status Register - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

15.3 Registers and Register Details

15.3.1 Timer control status register (TMCSR)

Timer control status register (upper)
Address: ch0 000049
ch1 00004D
ch2 000051
Read/write
Initial value
Timer control status register (lower)
Address: ch0 000048
ch1 00004C
ch2 000050
Controls the operation mode and interrupts for the 16-bit timer. Only modify bits other than UF, CNTE, and
TRG when CNTE = "0".
[Bits 11, 10] CSL1, CSL0 (Clock select 1, 0)
The count clock select bits. The following tMable lists the selected clock sources.LL
CSL1
210 Chapter 15: 16-Bit Reload Timer (with Event Count Function)
15

H

— —
H

H
— —
— —
7

H

MOD0 OUTE
H

H
Read/write
(R/W) (R/W)
(0) (0)
Initial value

Figure 15.3.1a Timer Control Status Register

CSL0
0 0
0 1
1 0
1 1
14 13 12 11
— — CSL1 CSL0
— — (R/W) (R/W)
— — (0)
6 5 4
OUTL RELD INTE
(R/W) (R/W) (R/W)
(0) (0) (0)
Clock Source (Machine cycle φ = 16 MHz)
φ/2 1 (0.125 µs)
φ/2 (0.5 µs)
3
φ/2 (2.0 µs)
5
External event count mode
10 9 8
MOD2 MOD1
(R/W) (R/W)
(0) (0) (0)
3 2 1
UF CNTE TRG
(R/W) (R/W) (R/W)
(0) (0) (0)
Bit number
TMCSR0-2
(HIGH)
Bit number
0
TMCSR0-2
(LOW)
MB90580 Series