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CHAPTER 5 CLOCK
5.5
Oscillation Stabilization Wait Interval
When the power is turned on, when stop mode is released, or when a watchdog timer
reset occurs, the oscillation clock starts, oscillation is unstable initially. Therefore, an
oscillation stabilization wait interval is required. When the switch from the main clock to
a PLL clock occurs, an oscillation stabilization wait interval is also required when PLL
oscillation starts.
■ Oscillation Stabilization Wait Interval
Ceramic and crystal oscillators generally require an oscillation stabilization wait interval of a few to several
dozen milliseconds until they stabilize at their natural frequency when oscillation starts.
For this reason, CPU operation is not allowed as soon as oscillation starts and is allowed only after full
stabilization of oscillation. After the oscillation stabilization wait interval has elapsed, the clock is supplied
to the CPU.
Because the oscillation stabilization time depends on the type of the oscillator (crystal, ceramic, etc.), the
proper oscillation stabilization wait interval for the oscillator used must be selected. An oscillation
stabilization wait interval is selected by setting the clock selection register (CKSCR).
In a switch from the main clock to a PLL clock, the CPU continues to operate on the main clock during the
oscillation stabilization wait interval. After this interval, the operating clock switches to the PLL clock.
Figure 5.5-1 shows the operation after oscillation starts.
86
Figure 5.5-1 Operation when Oscillation Starts
Oscillator-activated Oscillation stabilization Normal operation start
oscillation time
Start of oscillation
Stable oscillation
wait interval
or change to PLL clock
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