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CHAPTER 15 MULTI-PULSE GENERATOR
■ The Use of the 16-bit Timer in Multi-pulse Generator
The timer is reset when write timing or position detection interrupt flag is set, which is selectable by the
MODE bit in the Timer Control Status Register (TCSR).
The timer can be started or stopped by setting the TMEN bit in the Timer Control Status Register (TCSR).
There is no timer overflow interrupt. Whenever the timer is restarted, the current counter value is latched to
a buffer for speed calculation.
If the counter value is matched with Compare Clear Register (CPCR), it interrupts the CPU and the timer is
reset.
Note:
If the Compare Clear Register (CPCR) is loaded a value same as the Timer Counter value at that
moment, the comparison operation will NOT be performed until next same counter value.
The Compare Clear interrupt shares the same interrupt vector with the Write Timing interrupt while
Compare Match interrupt shares the same vector as that of the Position Detect interrupt.
■ 16-bit Timer in Multi-pulse Generator Operation Diagram
Figure 15.6-32 16-bit Timer in Multi-pulse Generator Operation Diagram
Compare
Clear
Register
(CPCR)
Timer is reset, which is triggered
by write timing or position detection.
428
Counter value
Timer is reset, which is triggered
by write timing or position detection.
If no desired position
detect signal appears
for a timeout period,
it means abnormal.
Current counter
value is latched
into buffer.
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