Input Control Register (Ipcr) - Fujitsu MB90460 Series Hardware Manual

CHAPTER 15 MULTI-PULSE GENERATOR
15.4.4

Input Control Register (IPCR)

The Input Control Register (IPCR) is a register which sets the control of the position
detection inputs.
■ Input Control Upper Register (IPCUR)
Address bit 15
00008D WTS1 WTS0
H
R/W R/W
X : Indeterminate
R/W : Readable and writable
: Initial value
— : Not used
384
Figure 15.4-8 Input Control Upper Register (IPCUR)
14 13 12 11
CPIF CPIE CPD2
R/W R/W R/W
WTS1
0
0
1
1
10 9 8 Initial value
CPD1 CPD0 CMPE 00000000
R/W R/W R/W
CMPE Position detection comparison enable bit
0 Disable comparison operation. (Initial value)
1
CPD2 CPD1 CPD0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
CPIE Comparison interrupt request enable bit
0
1
Comparison interrupt request flag bit
CPIF
0 No valid detected.
1 Valid detected.
WTS0 Write timing and PPG synchronization selection bits
0 No synchronization. (Initial value)
1 Rising edge synchronization. ↑
Falling edge synchronization. ↓
0
Both edges synchronization. ↑ & ↓
1
B
Enable comparison operation.
Comparsion bits
Compare match if RDA2 to RDA0 = 000.
Compare match if RDA2 to RDA0 = 001.
Compare match if RDA2 to RDA0 = 010.
Compare match if RDA2 to RDA0 = 011.
Compare match if RDA2 to RDA0 = 100.
Compare match if RDA2 to RDA0 = 101.
Compare match if RDA2 to RDA0 = 110.
Compare match if RDA2 to RDA0 = 111.
Disable interrupt. (Initial value)
Enable interrupt.
Read Write
Clear this bit.
No effect.