Fujitsu MB90460 Series Hardware Manual page 114

Table 6.3-1 Function Description of Each Bit of the Low Power Consumption Mode Control Register
(LPMCR)
Bit name
STP:
bit7
Stop bit
SLP:
bit6
Sleep bit
SPL:
Pin state setting bit (for
bit5
time-base timer mode and
stop mode)
RST:
bit4 Internal reset signal
generation bit
TMDX:
bit3
Time-base timer bit
CG1, CG0:
bit2,
CPU halt clock pulses
bit1
selection bits
RESV:
bit0
Reserved bit
Note:
If "1" is written to the STP bit, SLP bit and "0" is written to TMDX bit at the same time, switching to
stop mode takes the highest priority, then time-base timer mode and sleep mode has the lowest
priority.
CHAPTER 6 LOW POWER CONSUMPTION MODE
• This bit indicates switching to stop mode.
• When "1" is written to this bit, a switch to stop mode.
• Writing "0" to this bit has no effect on operation.
• This bit is cleared to "0" by a reset or by release of stop state.
• The read value of this bit is always "0".
• This bit indicates switching to sleep mode.
• When "1" is written to this bit, the mode switches to sleep mode.
• Writing "0" to this bit has no effect on operation.
• This bit is cleared to "0" by a reset or by release of sleep mode.
• The read value of this bit is always "0".
• This bit is enabled while either time-base timer mode or stop mode is in effect.
• When this bit is "0", the level of the external pins is retained.
• When this bit is "1", the status of the external pins changes to high- impedance.
• This bit is initialized to "0" by a reset.
• When "0" is written to this bit, an internal reset signal of 3 machine cycles is
generated.
• Writing "1" to this bit has no effect on operation.
• The read value of this bit is always "1".
• This bit indicates switching to time-base timer mode.
• When "0" is written to this bit, the mode switches to time-base timer mode.
• Writing "1" to this bit has no effect on operation.
• This bit is set to "1" by a reset or by release of time-base timer mode.
• The read value of this bit is always "1".
• These bits set the number of CPU halt clock pulses for the CPU intermittent
operation function.
• The clock supplied to the CPU is stopped after the execution of every instruction
for the specified number of clock pulses.
• Selection can be made from among four different clock pulses.
• These bits are initialized to 00
resets do not initialize these bits.
(Note)
"1" must always be written to this bit.
Function
by a power-on or watchdog timer reset. Other
B
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