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CHAPTER 15 MULTI-PULSE GENERATOR
■ DTTI1 Circuit Timing Diagram (D1,D0 = 00
φ
DTTI1
DTIE*
NRSL
DTIF
DTISP
DTTI1
DTIE
NRSL
DTIF*
DTISP
* DTIF goes to low only by writing a "0" to it.
Note:
In worst case the time from DTTI1 being recognized (after noise cancellation) to DTISP in effect
takes 2 cycles, in best case it takes 1 cycle.
422
Figure 15.6-26 DTTI1 Circuit Timing Diagram (D1,D0 = 00
4 Cycles
)
B
)
B
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