Overview Of The Watchdog Timer - Fujitsu MB90460 Series Hardware Manual

CHAPTER 11 WATCHDOG TIMER
11.1

Overview of the Watchdog Timer

The watchdog timer is a 2-bit counter that uses the time-base timer supply clock as the
count clock. After activation, if the watchdog timer is not cleared within a given time,
the CPU is reset.
■ Watchdog Timer Function
The watchdog timer is a counter for handling program crashes. Once the watchdog timer is activated, it
must be regularly cleared within a given time. If the program results in an endless loop and the watchdog
timer is not cleared over a given time, a watchdog reset is generated for the CPU.
Table 11.1-1 lists the watchdog timer intervals. If the watchdog timer is not cleared, a watchdog reset is
generated between the minimum time and maximum time. Clear the counter within the minimum time
listed in this table.
Table 11.1-1 Intervals for the Watchdog Timer
* Value during operation of the 4 MHz oscillation clock
The maximum and minimum watchdog timer intervals and the oscillation clock cycle count depend on the
clear timing.
The interval is 3.5 to 4.5 times longer than the cycle of the count clock (time-base timer supply clock).
See "11.4 Operation of the Watchdog Timer".
Note:
The watchdog counter consists of a 2-bit counter that uses the carry signals of the time-base timer
as count clocks. Therefore, if the time-base timer is cleared, the watchdog reset generation time
may become longer than the time set.
Reference:
At activation, the watchdog timer is initialized by a power-on or watchdog reset, and is placed in
stopped status. The watchdog timer is cleared by an external pin reset, software reset, writing to the
WTE bit (watchdog timer control register), sleep mode or transition to stop mode. However, It is not
stopped.
220
Minimum*
Approx. 3.58 ms
Approx. 14.33 ms
Approx. 57.23 ms
Approx. 458.75 ms
Interval
Maximum*
Approx. 4.61 ms
Approx. 18.3 ms
Approx. 73.73 ms
Approx. 589.82 ms
Oscillation clock cycle count
14 11
2 ±2 cycle
16 13
2 ±2 cycle
18 15
2 ±2 cycle
21 18
2 ±2 cycle