Event Count Mode - Fujitsu MB90460 Series Hardware Manual

CHAPTER 12 16-BIT RELOAD TIMER
12.6.3

Event Count Mode

The 16-bit reload timer counts an input edge from the TIN0/TIN1 pin, counts down the
16-bit counter, and generates an interrupt request to the CPU for a counter underflow. It
can also output a toggle waveform or rectangular waveform from the TO0/TO1 pin.
■ Event Count Mode
When counting is enabled (TMCSRL0/TMCSRL1:CNTE = 1) and the counter is started (TMCSRL0/
TMCSRL1:TRG = 1), the value of the reload register is loaded into the counter. Counting down is then
done every time a valid edge (rising, falling, and both edges can be selected) of the pulse input to the TIN
pin (external count clock) is detected.
When the count enable bit and software trigger bit are set to "1" simultaneously, counting is started
simultaneously with the enabling of counting.
●
Operation in reload mode
When an underflow of the counter value (from 0000
(TMRD0/TMRD1) is loaded into the counter, and counting continues. If the underflow interrupt flag
(TMCSRL0/TMCSRL1:UF) bit is set to "1" and the underflow interrupt enable bit (TMCSRL0/
TMCSRL1:INTE) is "1", an interrupt request is generated.
The timer can also output from the TO0/TO1 pin a toggle waveform, which is inverted for each underflow.
Figure 12.6-10 shows counting in reload mode.
Figure 12.6-10 Count Operation in Reload Mode (Event Count Mode)
Data load signal
CNTE bit
T: Machine cycle
* It takes 1T time from trigger input to loading of the reload data.
Note:
Specify 4/φ or more for the H and L widths of the clock input to the TIN0/TIN1 pin.
250
TIN pin
Reload data
Counter
UF bit
TRG bit
TO pin
to FFFF
H
Reload data
Reload data
) occurs, the value of the reload register
H
Reload data