Fujitsu MB90460 Series Hardware Manual page 102

Table 5.3-1 Function Description of Each Bit of the Clock Selection Register (CKSCR)
Bit name
bit15, RESV:
bit11 Reserved bit
MCM:
bit14
Machine clock indication bit
WS1, WS0:
bit13, Oscillation
bit12 stabilization wait interval
selection bits
MCS:
bit10
Machine clock selection bit
CS1, CS0:
bit9,
Multiplier
bit8
selection bits
HCLK: Oscillation clock frequency
(Note)
"1" must always be written to these bits.
• This bit indicates whether the main clock or a PLL clock has been selected as
the machine clock.
• When this bit is set to "0", a PLL clock has been selected. When it is set to "1",
the main clock has been selected.
• If MCS = 0 and MCM = 1, the PLL clock oscillation stabilization wait period is
in effect.
• Writing has no effect on the operation.
• These bits select an oscillation stabilization wait interval of the oscillation clock
after stop mode has been released.
• These bits are initialized to 11
(Note)
The oscillation stabilization wait interval must be set to a value appropriate for
the oscillator used. See "4.2 Reset Causes and Oscillation Stabilization Wait
Intervals".
(Reference)
The oscillation stabilization period for all PLL clocks is fixed at 2
• This bit specifies whether the main clock or a PLL clock is selected as the
machine clock.
• When this bit is "0", a PLL clock is selected. When this bit is "1", the main
clock is selected.
• If this bit has been set to "1" and "0" is written to it, the oscillation stabilization
wait interval for the PLL clock starts. As a result, the time-base timer is auto-
matically cleared, and the TBOF bit of the time-base timer control register
(TBTC) is also cleared.
• For PLL clocks, the oscillation stabilization period is fixed at 2
(the oscillation stabilization wait interval is approx. 2 ms for an oscillation clock
frequency of 4 MHz).
• When the main clock has been selected, the operating clock frequency is the fre-
quency of the oscillation clock divided by 2 (e.g., the operating clock is 2 MHz
when the oscillation clock frequency is 4 MHz).
• This bit is initialized to "1" by power-on or watchdog reset.
(Note)
When the MCS bit is "1", write "0" to it only when the time-base timer interrupt
is masked by the TBIE bit of the time-base timer control register (TBTC) or the
interrupt level register (ILM). For 8 machine cycles after "1" is written to the
MCS bit, writing "0" to it may be disabled. Write to the bit after 8 machine
cycles have passed.
• These bits select a PLL clock multiplier.
• Selection can be made from among four different multipliers.
• These bits are initialized to 00
(Note)
When the MCS bit is "0", writing to these bits is not allowed. Write to the CS1
and CS0 bits only after setting the MCS bit to "1" (main clock mode).
Function
by all reset causes.
B
by all reset causes.
B
CHAPTER 5 CLOCK
14
/HCLK.
14
/HCLK
83