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MB90335 Series
14.2.1
Timer Control Status Register 0 (TMCSR0)
Configuration and functions of timer control status registers 0 (TMCSR0) are described.
■ Timer Control Status Register 0 (TMCSR0)
The timer control status registers 0 (TMCSR0) control the operation mode and interrupt of 16-bit reload
timer. Bits other than UF/CNTE/TRG are modified at CNTE=0.
Figure 14.2-2 shows the bit configuration of timer control status registers 0 (TMCSR0).
Figure 14.2-2 Bit Configuration of Timer Control Status Registers 0 (TMCSR0)
ch.0 : 000063
ch.0 : 000062
R/W
X
The functions of each bit of timer control status registers 0 (TMCSR0) are described in the following:
[bit15 to bit12] Undefined bits
The reading value is undefined. No effect on writing.
[bit11, bit10] CSL1, CSL0 (clock selection)
Clock source is selected by count clock selection.
CSL1
0
0
1
1
CM44-10137-6E
bit
15
14
13
Address:
H
X
X
X
bit
7
6
5
Address:
MOD0 OUTE OUTL RELD INTE
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Readable/Writable
Undefined value
Undefined
CSL0
0
1
0
1
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 14 16-BIT RELOAD TIMER
14.2 Registers of 16-bit Reload Timer
12
11
10
9
CSL1 CSL0 MOD2 MOD1
X
(R/W) (R/W) (R/W) (R/W)
4
3
2
1
CNTE TRG
UF
Clock source (machine clock φ=24 MHz time)
φ/2
φ/2
φ/2
Event count mode
8
TMCSR0 (upper)
Initial value
XXXX0000
B
0
TMCSR0 (lower)
Initial value
00000000
B
1
(0.083 μs)
[Initial value]
3
(0.33 μs)
5
(1.33 μs)
323
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