Reset Causes And Oscillation Stabilization Wait Intervals - Fujitsu MB90460 Series Hardware Manual

F2mc-16lx 16-bit microcontroller
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CHAPTER 4 RESET
4.2

Reset Causes and Oscillation Stabilization Wait Intervals

2
The F
MC-16LX has four reset causes. The oscillation stabilization wait interval for a
reset depends on the reset cause.
■ Reset Causes and Oscillation Stabilization Wait Intervals
Table 4.2-1 and Figure 4.2-1 summarize reset causes and oscillation stabilization wait intervals.
Table 4.2-1 Reset Causes and Oscillation Stabilization Wait Intervals
Power-on reset
Watchdog timer
External reset via the RSTX pin
Software reset
HCLK: Oscillation clock frequency, source oscillation.
Figure 4.2-1 shows the oscillation stabilization wait interval of the product at power-on reset.
Figure 4.2-1 Oscillation Stabilization Wait Interval at Power-on Reset
Vcc
CLK
CPU operation
HCLK: oscillation clock
Note:
Ceramic and crystal oscillators generally require an oscillation stabilization wait interval of a few to
several dozen milliseconds until they stabilize at their natural frequency. Be sure to set a proper
oscillation stabilization wait interval for the specific oscillator used.
See "4.2 Reset Causes and Oscillation Stabilization Wait Intervals" for detail about Oscillation
Stabilization Wait Interval.
■ Oscillation Stabilization Wait and Reset State
A reset operation in response to a power-on reset and other externally activated resets during
stop mode and hardware standby mode is performed after the oscillation stabilization wait interval
has elapsed. This time interval is generated by the time-base timer. If the external reset has not
been cleared after the interval, the reset operation is performed after the external reset is cleared.
68
Reset cause
17
17
2
/HCLK
2
/HCLK
Regulator stabilization
Oscillation stabilization
wait interval
wait interval
Oscillation stabilization wait interval
The corresponding time interval for an oscillation clock
frequency of 4 MHz is given in parentheses.
18
2
/HCLK (approximately 65.54 ms)
17
2
/HCLK (approximately 32.77 ms)
None. However the WS1 & WS0 bits are initialized to "11".
None. However the WS1 & WS0 bits are initialized to "11".

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