Operation Of The Watchdog Timer - Fujitsu MB90460 Series Hardware Manual

CHAPTER 11 WATCHDOG TIMER
11.4

Operation of the Watchdog Timer

The watchdog timer generates a watchdog reset by an overflow of the watchdog
counter.
■ Watchdog Timer Operation
Operation of the watchdog timer requires the setting in Figure 11.4-1.
WDTC
: Used
0 : Set "0"
●
Activating the watchdog timer
• The watchdog timer is activated when the first 0 after reset is written to the WTE bit of the watchdog
timer control register (WDTC). Specify the interval by specifying the WT1 and WT0 bits of the
watchdog timer control register at the same time.
• When watchdog timer activation starts, it can be stopped only by a power-on or its own reset.
●
Clearing the watchdog timer
• When a second or subsequent "0" is written to the WTE bit, the 2-bit counter of the watchdog timer is
cleared. If the counter is not cleared within the time interval, it overflows and a watchdog reset occurs.
• The watchdog counter is cleared by reset generation, sleep mode or stop mode, transition to clock mode.
●
Intervals for the watchdog timer
Figure 11.4-2 shows the relationship between the clear timing of the watchdog timer and intervals. The
interval changes according to the clear timing of the watchdog timer and requires 3.5 to 4.5 times longer
than the count clock cycle.
●
Checking a reset cause
A reset cause can be determined by checking the PONR, WRST, ERST and SRST bits of the watchdog
timer control register (WDTC) after a reset.
224
Figure 11.4-1 Setting of the Watchdog Timer
7
8
bit 15
TBTC
PONR
6 5 4 3
- WRST ERST SRST WTE WT1 WT0
2 1 0
0