Fujitsu MB90460 Series Hardware Manual page 650

Table A-1 I/O Map (4/6)
Address Abbreviation
000070
OCCPB0 /
H
OCCP0
000071
H
000072
OCCPB1 /
H
OCCP1
000073
H
000074
OCCPB2 /
H
OCCP2
000075
H
000076
OCCPB3 /
H
OCCP3
000077
H
000078
OCCPB4 /
H
OCCP4
000079
H
00007A
OCCPB5 /
H
OCCP5
00007B
H
00007C
OCS0
H
00007D
OCS1
H
00007E
OCS2
H
00007F
OCS3
H
000080
OCS4
H
000081
OCS5
H
000082
TMCSRL0 Timer control status register CH.0 (lower byte)
H
000083
TMCSRH0 Timer control status register CH.0 (upper byte)
H
000084
TMR0 /
H
TMRD0
000085
H
000086
TMCSRL1 Timer control status register CH.1 (lower byte)
H
000087
TMCSRH1 Timer control status register CH.1 (upper byte)
H
000088
TMR1 /
H
TMRD1
000089
H
00008A
OPCLR
H
00008B
OPCUR
H
00008C
IPCLR
H
00008D
IPCUR
H
00008E
TCSR
H
00008F
NCCR
H
000090 to 9D
H H
00009E
PACSR
H
00009F
DIRR
H
0000A0
LPMCR
H
0000A1
CKSCR
H
0000A2
H
to A7
H
0000A8
WDTC
H
0000A9
TBTC
H
0000AA
H
to AD
H
0000AE
FMCS
H
0000AF
H
Register
Output compare buffer register / Output compare
register 0
Output compare buffer register / Output compare
register 1
Output compare buffer register / Output compare
register 2
Output compare buffer register / Output compare
register 3
Output compare buffer register / Output compare
register 4
Output compare buffer register / Output compare
register 5
Compare control register 0
Compare control register 1
Compare control register 2
Compare control register 3
Compare control register 4
Compare control register 5
16-bit timer register /
16-bit reload register CH.0
16-bit timer register /
16-bit reload register CH.1
Output control lower register
Output control upper register
Input control lower register
Input control upper register
Timer control status register
Noise cancellation control register
Program address detect control status register
Delayed interrupt cause / clear register
Low-power consumption mode register
Clock selection register
Watchdog control register
Time-base timer control register
Flash memory control status register
Byte access Word access Resource name
- R/W
- R/W
- R/W
- R/W
- R/W
- R/W
R/W R/W
R/W R/W
R/W R/W
R/W R/W
R/W R/W
R/W R/W
R/W R/W
R/W R/W
- R/W
R/W R/W
R/W R/W
- R/W
R/W R/W
R/W R/W
R/W R/W
R/W R/W
R/W R/W
R/W R/W
Prohibited area
R/W R/W
R/W R/W
R/W R/W
R/W R/W
Prohibited area
R/W R/W
R/W R/W
Prohibited area
R/W R/W
Prohibited area
APPENDIX A I/O MAP
Initial value
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Output compare
(CH.0 to CH.5)
XXXXXXXX
XXXXXXXX
XXXXXXXX
00000000
B
-0000000
B
00000000
B
-0000000
B
00000000
B
-0000000
B
00000000
B
----0000
16-bit reload timer
B
(CH.0)
XXXXXXXX
XXXXXXXX
00000000
B
----0000
16-bit reload timer
B
(CH.1)
XXXXXXXX
XXXXXXXX
00000000
B
00000000
B
00000000
Waveform
B
sequencer*
00000000
B
00000000
B
00000000
B
Address match
----0000
B
detection
-------0
Delayed interrupt
B
Low-power 00011000
B
consumption
11111100
B
control register
X-XXX111
Watchdog timer
1--00100
Time-base timer
B
Flash memory
00010000
B
interface circuit
631
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B