Fujitsu MB90460 Series Hardware Manual page 431

F2mc-16lx 16-bit microcontroller
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CHAPTER 15 MULTI-PULSE GENERATOR
The comparisons between pin SNI2 and RDA2 bit, pin SNI1 and RDA1 bit, pin SNI0 and RDA0 bit are
done for each position detection.
The OPTx output waveform is updated according to the effective edge input to pin SNIx as shown in
Figure 15.6-17. The data of the Output Data Buffer Register (OPDBR) specified by the BNKF, RDA2 to
RDA0 bits is transferred to the Output Data Register (OPDR), and the output data is renewed automatically
when pins SNI2 to SNI0 are compared with the value of the RDA2 to RDA0 bits and matches.
The reload timer 0 is free to be used in this operation mode.
■ Timing Generated by Position Detection (OPS2 to OPS0 = 010
Figure 15.6-17 Timing Generated by Position Detection (OPS2 to OPS0 = 010
SNI2
SNI1
SNI0
RDA2 to
100
RDA0
(OPDR)
WTIN1
WTO
OP01,
00
OP00
(OPDR)
PPG
OPT0
412
110
101
11
01
)
B
011
001
00
10
)
B
11

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