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6.4
CPU Intermittent Operation Mode
CPU intermittent operation mode is used for intermittent operation of the CPU while
external buses and peripheral functions continue to operate at high speed. Its purpose
is to reduce power consumption.
■ CPU Intermittent Operation Mode
CPU intermittent operation mode halts the supply of the clock to the CPU for a certain period. The halt
occurs after the execution of every instruction that accesses a register, internal memory (ROM and RAM),
I/O, peripheral functions and the external bus. Internal bus cycle activation is therefore delayed. While a
steady rate of peripheral clock pulses are supplied to the peripheral functions, the rate of CPU execution is
reduced, enabling processing with low power consumption.
• The CG1 and CG0 bits of the low power consumption mode control register (LPMCR) are used to select
the number of clock pulses per halt cycle of the clock supplied to the CPU.
• External bus operation uses the same clock as that used for peripheral functions.
• Instruction execution time in CPU intermittent mode can be calculated. A correction value should be
obtained by multiplying the number of times instructions that access a register, internal memory,
internal peripheral functions, and the external bus are executed by the number of clock pulses per halt
cycle. Add this correction value to the normal execution time.
Figure 6.4-1 shows the operating clock pulses during CPU intermittent operation mode.
Peripheral clock
CPU clock
Figure 6.4-1 Clock Pulses during CPU Intermittent Operation
Intermittent operation halt cycle
CHAPTER 6 LOW POWER CONSUMPTION MODE
One instruction
execution cycle
Internal bus activation cycle
97
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