Fujitsu MB90460 Series Hardware Manual page 315

CHAPTER 14 MULTI-FUNCTIONAL TIMER
Table 14.4-1 Timer Control Status Register (TCCSH)
Bit name
ECKE:
bit15
Clock selection bit
IRQZF:
bit14 Zero detect
interrupt flag bit
IRQZE:
Zero detect
bit13
interrupt request
enable bit
bit12 MSI2 to MSI0:
to Interrupt mask
bit10 selection bits
ICLR:
bit9 Compare clear
interrupt flag bit
ICRE:
Compare clear
bit8
interrupt request
enable bit
296
• This bit is used to select internal or external clock as count clock for 16-bit free-run
timer.
• Writing "0" selects internal clock. The clock frequency selection bits (CK2 to CK0)
should also be set to select the count clock frequency.
• Writing "1" selects external clock. External clock is input from pin "P17/FRCK", so
DDR1:7 should be set as "0" to enable external clock input.
(Note)
The count clock is changed immediately after this bit is set. So change this bit while the
output compare and input capture units are stopped.
• This bit is an interrupt flag for zero detect.
• When the count value of 16-bit free-run timer is "0000
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
(Note)
• In software clear, (writing TCCSL:SCLR "1") will not set this bit.
• In up-down count mode (MODE=1) and interrupt mask function is selected (MSI2
to MSI0 not equals 000
masked.
• In up-count mode (MODE=0), this bit is set at every zero detect disregarding the
value of MSI2 to MSI0.
• This is the interrupt request enable bit for the zero detect.
• When this bit is "1" and the interrupt flag (bit14: IRQZF) is set to "1", an interrupt
request will be generated to CPU.
• These bits are used to set the number of times of masking the compare clear interrupt in
up-count mode (MODE=0) or zero detect interrupt in up-down count mode
(MODE=1).
• No interrupt cause is masked when MSI2 to MSI0 equals zero.
(Note)
To mask the interrupt cause twice and perform interrupt processing at the third time,
MSI2 to MSI0 should be set as 010
• This bit is an interrupt flag for compare clear.
• When the compare clear value and 16-bit free-run timer value are matched, this bit is
set to "1".
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
(Note)
• In up-count mode (MODE=0) and interrupt mask function is selected (MSI2 to
MSI0 not equals 000B), this bit will only be set after the number of compare clear is
masked.
• In up-down count mode (MODE=1), this bit is set at every compare clear
disregarding the value of MSI2 to MSI0.
• This is the interrupt request enable bit for the compare clear.
• When this bit is "1" and the interrupt flag (bit9: ICLR) is set to "1", an interrupt request
will be generated to CPU.
Function
), this bit will only be set after the number of zero detect is
B
.
B
", this bit is set to "1".
H