Fujitsu MB90460 Series Hardware Manual page 321

CHAPTER 14 MULTI-FUNCTIONAL TIMER
Table 14.4-3 Compare Control Register (OCS1/OCS3/OCS5) bit
Bit name
bit15 Unused bit
bit14 BTS1
bit13 BTS0
CMOD:
bit12 Output level
reverse mode bit
OTE1:
bit11 Output enable
bit
OTE0:
bit10 Output enable
bit
OTD1:
bit9
Output level bit
OTD0:
bit8
Output level bit
302
• The read value is indeterminate.
• Writing to this bit has no effect on the operation.
• This bit is used to select when data transfer from output compare buffer register (OCCPB1/
OCCPB3/OCCPB5) to output compare register (OCCP1/OCCP3/OCCP5).
• When BTS1=0, buffer transfer is occurred when count value of 16-bit free-run timer is
detected as zero.
• When BTS1=1, buffer transfer is occurred when compare clear match is occurred in 16-bit
free-run timer.
• This bit is used to select when data transfer from output compare buffer register (OCCPB0/
OCCPB2/OCCPB4) to output compare register (OCCP0/OCCP2/OCCP4).
• When BTS0=0, buffer transfer is occurred when count value of 16-bit free-run timer is
detected as zero.
• When BTS0=1, buffer transfer is occurred when compare clear match is occurred in 16-bit
free-run timer.
• CMOD is used to switch the pin output level reverse mode upon a match while pin output is
enabled (OTE1 = 1 or OTE0 = 1).
• When CMOD = 0, the output level of the pin is reversed upon a match with corresponding
compare register.
RT0/RT2/RT4: The level is reversed upon a match between the 16-bit free-run timer and compare
register 0/2/4.
RT1/RT3/RT5: The level is reversed upon a match between the 16-bit free-run timer and compare
register 1/3/5.
• When CMOD = 1, the output level of the pin RT0/RT2/RT4 corresponding to compare register
is reversed as same as when CMOD = 0. However, the output level of the pin (RT1/RT3/RT5)
corresponding to compare register 1/3/5 is reversed when a match is detected in compare
register 0/2/4 or 1/3/5. If compare registers 0/2/4 and 1/3/5 have the same value, the same
operation as when only one compare register is used.
RT0/RT2/RT4: The level is reversed upon a match between the 16-bit free-run timer and compare
register 0/2/4.
RT1/RT3/RT5: The level is reversed upon a match between the 16-bit free-run timer and compare
register (0 or 1)/(2 or 3)/(4 or 5).
• This bit is used to enable waveform generator output RTO1/RTO3/RTO5 to P31/P33/P35.
• The initial value for these bits is "0".
(Note)
If waveform generator is disabled (DTCR:TMD2 to TMD0=000
same value in output compare RT1/RT3/RT5.
• This bit is used to enable waveform generator output RTO0/RTO2/RTO4 to P30/P32/P34.
• The initial value for these bits is "0".
(Note)
If waveform generator is disabled (DTCR:TMD2 to TMD0=000
same value in output compare RT0/RT2/RT4.
• This bit is used to change the output level for output compare 1/3/5 (RT1/RT3/RT5).
• The initial value of the compare output is "0".
• Ensure that the compare operation is stopped before a value is written. When reading this bit,
this bit indicate the output compare value in RT1/RT3/RT5.
• This bit is used to change the output level for output compare 0/2/4 (RT0/RT2/RT4).
• The initial value of the compare output is "0".
• Ensure that the compare operation is stopped before a value is written. When reading this bit,
this bit indicates the output compare value in RT0/RT2/RT4.
Function
) RTO1/RTO3/RTO5 output the
B
) RTO0/RTO2/RTO4 output the
B