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CHAPTER 17 UART
17.5
UART Interrupts
UART uses both reception and transmission interrupts. An interrupt request can be
generated for either of the receive data is set in the input register (SIDR0/SIDR1), or a
reception error occurs and transmission data is transferred from output data register 1
(SODR0/SODR1) to the transmission shift register.
The extended intelligent I-O service (EI
■ UART Interrupts
Table 17.5-1 lists the interrupt control bits and causes of UART
Table 17.5-1 Interrupt Control Bits and Interrupt Causes of UART
Reception/
Interrupt
transmission
request flag bit
RDRF
Reception
ORE
FRE
PE
Transmission
TDRE
O: Used
X: Not used
●
Reception interrupt
If one of the following events occurs in reception mode, the corresponding flag bit of the status register is
set to "1":
• Data reception is complete (SSR0/SSR1: RDRF)
• Overrun error (SSR0/SSR1: ORE)
• Framing error (SSR0/SSR1: FRE)
• Parity error (SSR0/SSR1: PE)
When at least one of the flag bits is "1" and the reception interrupts are enabled (SSR0/SSR1: RIE = 1), a
reception interrupt request is output to the interrupt controller.
When the input data register (SIDR0/SIDR1) is read, the receive data full flag (SSR0/SSR1: RDRF) is
automatically cleared to "0". When "0" is written to the REC bit of the control register (SCR0/SCR1), all
the reception error flags (SSR0/SSR1: PE, ORE and FRE) are cleared to "0".
486
2
OS) is available for these interrupts.
Operation mode
Interrupt cause
0
1
2
Loading receive data
O
O
O
into buffers (SIDR0/
SIDR1)
O
O
O
Overrun error
O
O
X
Framing error
O
X
X
Parity error
Empty transmission
O
O
O
buffer (SODR0/
SODR1)
Interrupt cause
When interrupt request
enable bit
flag is cleared
Receive data is read
SSR0/SSR1:RIE
0 is written to the
reception error flag clear
bit (SSR0/SSR1: REC)
Transmission data is
SSR0/SSR1:TIE
written
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