Figure 5.3 Timebase Timer Control Register (Tbtc) - Fujitsu F2MC-8L MB89620 Series Hardware Manual

3
5. Timebase Timer Control Register (TBTC)
The timebase timer control register (TBTC) is used to select the interval timer bit, clear
the counter, control interrupts, and check the state of the timebase timer.
n Timebase Timer Control Register (TBTC)
Address
000A
H
R/W : Readable and writable
W
—
X
120
CHAPTER 5 TIMEBASE TIMER
Bit 7 Bit 6 Bit 5
— — —
: Write-only
: Unused
: Indeterminate
: Initial value

Figure 5.3 Timebase Timer Control Register (TBTC)

Bit 4 Bit 3 Bit 2 Bit 1
TBIE TBOF TBR TBC1
R/W R/W W R/W
TBC1 TBC0
0 0
0 1
1 0
1 1
F : Source oscillation
C
TBR
0
Reading always returns
1
"1".
TBOF
No overflow on specified
0
bit
1 Overflow on specified bit
TBIE
0 Disables interrupt request output.
1 Enables interrupt request output.
Bit 0 Initial value
TBC0 XXX00000
B
R/W
Interval time selection bits
2 15 /F
C
17
2 /F
C
2 19 /F
C
2 21 /F
C
Timebase timer initialization bit
Read
Clears the timebase timer
—
counter.
No effect. The bit does not
change.
Overflow interrupt request flag bit
Read
Clears this bit.
No effect. The bit does not
change.
Interrupt request enable bit
Write
Write
MB89620 series