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Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a high-
impedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR3 register. Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit.
Table 9.6-4 lists the states of the port 3 pins.
Table 9.6-4 States of Port 3 Pins
Pin
Normal operation
P30/RTO0
General-purpose I/O port General-purpose I/O port
to P37/PPG0
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z: High impedance
Stop mode or time-base
Sleep mode
timer mode (SPL = 0)
General-purpose I/O port
CHAPTER 9 I/O PORT
Stop mode or time-base
timer mode (SPL = 1)
Input shut down/output in
Hi-Z
187
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