Fujitsu MB90460 Series Hardware Manual page 104

Figure 5.4-1 shows the status change caused by the machine clock switching.
Figure 5.4-1 Status Dhange Diagram for Machine Dlock Selection
Main
MCS = 1
MCM = 1
CS1, CS0 = xx
(1) The MCS bit is cleared.
(2) The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 00.
(3) The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 01.
(4) The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 10.
(5) The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 11.
(6) The MCS bit is set (including also hardware standby and watchdog timer resets).
(7) PLL clock and main clock synchronization timing.
MCS:
Machine clock selection bit of CKSCR
MCM: Machine clock indication bit of CKSCR
CS1, CS0:
Multiplier selection bits of CKSCR
Note:
The initial value for the machine clock setting is main clock (MCS of CKSCR = 1).
Power-on
(1)
(2)
Main PLLx
(3)
MCS = 0
(4)
MCM = 1
(5)
(6)
CS1, CS0 = xx
(7)
PLL1 Main
MCS = 1
MCM = 1
CS1, CS0 = 00
(7)
PLL2 Main
MCS = 1
MCM = 0
CS1, CS0 = 01
(7)
PLL3 Main
MCS = 1
(6)
MCM = 0
CS1, CS0 = 11
(7)
PLL4 Main
MCS = 1
(6)
MCM = 0
CS1, CS0 = 11
CHAPTER 5 CLOCK
PLL1: Multiplied
by 1
MCS = 0
(6)
MCM = 0
CS1, CS0 = 00
PLL2: Multiplied
by 2
MCS = 0
(6)
MCM = 0
CS1, CS0 = 01
PLL3: Multiplied
by 3
MCS = 0
MCM = 0
CS1, CS0 = 10
PLL4: Multiplied
by 4
MCS = 0
MCM = 0
CS1, CS0 = 11
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