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10.4
Time-base Timer Interrupts
The time-base timer can generate an interrupt request when the bit specifying the time-
base timer counter overflows.
■ Time-base Timer Interrupts
The interrupt request flag bit (TBTC: TBOF) is set to "1" when the time-base timer counter counts up with
the internal count clock and when the bit for the selected interval timer bit overflows. If the interrupt
request enable bit has been enabled (TBTC: TBIE = 1), an interrupt request (#36) is generated in the CPU.
Write "0" to the TBOF bit in the interrupt handling routine to clear the interrupt request. When the
specified bit overflows, the TBOF bit is set regardless of the TBIE bit value.
Note:
Clear the interrupt request flag bit (TBTC: TBOF) while a time-base timer interrupt is disabled by
setting the TBIE bit or the processor status (PS) ILM bit.
Reference:
When the TBOF bit is "1", if the TBIE bit status is switched from disable to enable (0 -> 1), an
interrupt request occurs immediately.
■ Time-base Timer Interrupts and EI
Table 10.4-1 lists the time-base timer interrupt and EI
Table 10.4-1 Time-base Interrupts and EI
Interrupt number
#36 (24
)
H
∆: Usable when an interrupt cause that shares the ICR is not used.
Note:
ICR12 is common to the time-base timer interrupt and input capture channels 2/3 interrupt.
Interrupts can be used for two applications, but the interrupt level is the same.
2
OS
2
OS
Interrupt level setting register
Register name
Address
0000BC
ICR12
CHAPTER 10 TIME-BASE TIMER
2
OS.
Vector table address
Lower
Upper
FFFF6C
FFFF6D
H
H
2
EI
OS
Bank
∆
FFFF6E
H
H
211
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