Sleep Mode - Fujitsu MB90460 Series Hardware Manual

6.5.1

Sleep Mode

Sleep mode causes the CPU operating clock to stop while other components continue
to operate.
When the low power consumption mode control register (LPMCR) indicates a switch to
sleep mode, a switch to PLL sleep mode occurs if PLL clock mode has been set.
Alternatively, a switch to main sleep mode occurs if main clock mode has been set.
■ Switching to Sleep Mode
Writing "1" to the SLP and TMDX bit of LPMCR and 0 to the STP bit of LPMCR triggers a switch to sleep
mode.
At this time, if the MCS bit of the clock selection register (CKSCR) is "0", the microcontroller enters PLL
sleep mode. If the MCS bit of CKSCR is "1", the microcontroller enters main sleep mode.
Note:
Since the STP/TMDX bit setting overrides the SLP bit setting when "1" is written to the SLP, STP
and "0" to TMDX bit at the same time, the mode switches to stop/time-base timer mode.
●
Data retention function
In sleep mode, the contents of dedicated registers, such as accumulators and internal RAM, are retained.
●
Operation during an interrupt request
Writing "1" to the SLP bit of LPMCR during an interrupt request does not trigger a switch to sleep mode.
If the CPU does not accept the interrupt, the CPU executes the next instruction. If the CPU accepts the
interrupt, CPU operation immediately branches to the interrupt processing routine.
●
Status of pins
During sleep mode, all pins retain the state they had immediately before the switch to sleep mode. The
once exceptions are the pins used for bus input/output or bus control.
■ Release of Sleep Mode
The low power consumption control circuit releases sleep mode. Releasing is caused by the input of a reset
or by an interrupt.
●
Return to normal mode by a reset
When sleep mode is released by a reset, the microcontroller is placed in the reset state on release from sleep
mode.
CHAPTER 6 LOW POWER CONSUMPTION MODE
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