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CHAPTER 10 TIME-BASE TIMER
10.6
Usage Notes on the Time-base Timer
Notes about the effects on peripheral functions of clearing interrupt requests and the
time-base timer are given below.
■ Time-base Timer Usage Notes
●
Clearing interrupt requests
The TBOF bit of the time-base timer control register must be cleared while a time-base timer interrupt is
masked by the TBIE bit or the interrupt level mask register (ILM) of the processor status (PS).
●
Effects of time-base timer clearing
Clearing of the time-base timer counter affects the following operations:
• When the time-base timer is using the interval timer function (interval interrupt)
• When the watchdog timer is being used
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Use of the time-base timer as the oscillation stabilization time timer
At power-on, the source oscillation of the main clock stops in main stop mode. After oscillator operation
starts, the operating clock supplied by the time-base timer is used to take the oscillation stabilization wait
time of the main clock. An appropriate oscillation stabilization wait time must be selected based on the
type of oscillating element connected to the main clock oscillator (clock generation section). See "5.5
Oscillation Stabilization Wait Interval", for details.
●
Notes on peripheral functions to which clocks are supplied from the time-base timer
In the mode in which the main clock source oscillation stops, the counter is cleared and time-base timer
operation stops. When the time-base timer counter is cleared, the clock supplied from the time-base timer
is supplied from its initial state. As a result, the H level is shortened and the L level lengthened 1/2 cycle.
Although the clock for the watchdog timer is also supplied from its initial state; the watchdog timer
operates in normal cycles because the watchdog timer counter is cleared at the same time.
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