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CHAPTER 6 LOW POWER CONSUMPTION MODE
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Return to normal mode by an interrupt
If an interrupt request higher than level 7 is issued from a peripheral circuit during sleep mode, sleep mode
is released. After release, the CPU handles the interrupt as it would any other interrupt. The CPU executes
processing according to the settings of the I flag of the condition code register (CCR), interrupt level mask
register (ILM), and interrupt control register (ICR). If that interrupt is accepted, the CPU executes interrupt
processing. If the interrupt is not accepted, the CPU resumes execution with the instruction that follows the
instruction in which switching to sleep mode was specified.
Figure 6.5-1 shows the release of sleep mode for an interrupt.
Interrupt from a peripheral circuit
Enable flag is set
INT occurs
Interrupt execution
Note:
When interrupt processing is executed normally, the CPU first executes the instruction that follows
the instruction in which switching to sleep mode was specified. The CPU then proceeds to interrupt
processing.
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Return to normal mode from PLL sleep mode by an external reset
During PLL sleep mode, the main clock and the PLL clock generate clock pulses. Since an external reset
does not initialize the MCS bit in the clock selection register (CKSCR) to "1", PLL clock mode remains
selected (MCS of CKSCR = 0). On return from PLL sleep mode by an external reset, the CPU starts
operation using the PLL clock immediately after PLL sleep mode is released as shown in Figure 6.5-2.
100
Figure 6.5-1 Release of Sleep Mode for an Interrupt
NO
(IL < 7)
YES
YES
I = 0
NO
YES
ILM < IL
NO
Sleep mode is not
released
Execution of the
next instruction
Execution of the
next instruction
Sleep mode is not
released
Sleep mode is
released
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