Multiple Interrupts - Fujitsu MB90460 Series Hardware Manual

7.4.4

Multiple Interrupts

Multiple hardware interrupts can be implemented by setting different interrupt levels in
the interrupt level setting bits (IL0, IL1, IL2) of the interrupt control register (ICR) in
response to multiple interrupt requests from peripheral functions. Use of multiple
interrupts, however, is not possible with the extended intelligent I/O service.
■ Multiple Interrupts
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Operation of multiple interrupts
During execution of an interrupt processing routine, if an interrupt request with a higher-priority interrupt
level is generated, the current interrupt processing is interrupted and the interrupt request with the higher-
priority interrupt level is accepted. When the interrupt request with the higher-priority interrupt level
terminates, the CPU returns to the previous interrupt processing.
0 to 7 can be set as the interrupt level. If level 7 is set, the CPU does not accept interrupt requests.
During execution of interrupt processing, if an interrupt request with the same or lower-priority interrupt
level is generated, the new interrupt request is held until the current interrupt terminates unless the I flag or
ILM is changed.
Other multiple interrupts to be activated during an interrupt can be temporarily disabled by setting the I flag
in the condition code register (CCR) in the interrupt processing routine to interrupts not allowed (CCR: I =
0) or the interrupt level mask register (ILM) to interrupts not allowed (ILM = 000
Note:
The extended intelligent I/O service (EI
During processing of the extended intelligent I/O service (EI
extended intelligent I/O service requests are held.
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Example of multiple interrupts
This example of multiple interrupt processing assumes that a timer interrupt is given a higher priority than
an A/D converter interrupt. In this example, the A/D converter interrupt level is set to "2", and the timer
interrupt level is set to "1". If a timer interrupt is generated during processing of the A/D converter
interrupt, the processing shown in Figure 7.4-5 is performed.
2
OS) cannot be used for the activation of multiple interrupts.
2
OS), all other interrupt requests and
CHAPTER 7 INTERRUPT
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