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CHAPTER 15 MULTI-PULSE GENERATOR
■ 16-bit Timer Timing
The 16-bit timer is incremented based on the prescaler clock and counts up at a rising edge.
Note:
Before the prescaler clock is changed, the Timer Counter should be disable first by setting the
TMEN bit to "0".
CPU clock
Prescaler clock
Counter value
The counter can be cleared upon a reset, software clear (TCLR), a match with Compare Clear Register, the
Write Timing signal or the Position Detection signal. By a reset, the counter is immediately cleared. By a
match with Compare Clear Register, software clear (TCLR), the Write Timing signal or the Position
Detection signal, the counter is cleared in synchronization with the count timing.
φ
Compare
register value
Prescaler clock
Compare match
Counter value
426
Figure 15.6-29 16-bit Timer Count Timing
N+1
N
Figure 15.6-30 16-bit Timer Clear Timing
N - 1
N
N+2
N
0000
H
N+3
N+4
0001
0002
H
H
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