Fujitsu MB90460 Series Hardware Manual page 359

F2mc-16lx 16-bit microcontroller
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CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ PPG0 Output Control
PPG0 output to RTO0 to RTO5 can be enabled by PGEN0 to PGEN5 in PPG output control/input capture
control status register (PICSH01).
■ Gate Triggered PPG0 Output
In waveform generator, a GATE signal can be generated by using real-time outputs RT0 to RT5 or cope
with 16-bit timers 0/1/2 to trigger PPG0 counting. When 16-bit timer is used, two real-time outputs RT0/
RT2/RT4 and RT1/RT3/RT5 is operated with one 16-bit timer 0/1/2 to generate six individual gate signal.
And these six gate signals are logically OR to generate a GATE signal to trigger PPG0 counting.
If PGEN0 to PGEN5 signal is also used, six different waveforms can be output to RTO0 to RTO5 by using
one PPG0 only.
■ Generating GATE Signal during Each RTx is at "H" Level when GTENx is active
(DTCR0/DTCR1/DTCR2:TMD2 to TMD0=001
Figure 14.6-22 Generating GATE Signal during RTx is at "H" Level
16-bit free-run timer
FFFF
BFFF
Count value
7FFF
3FFF
0000
Compare register 0
value
Compare register 1
value
RT0
RT1
GATE0
GATE1
GATE
340
H
H
H
H
H
BFFF
H
7FFF
H
or 111
)
B
B
Time

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