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7.6.3
Operation of the Extended Intelligent I/O Service (EI
If an interrupt request is generated by a peripheral function, EI
the corresponding interrupt control register (ICR) that the CPU uses EI
data. When the specified data transfer count terminates, the hardware interrupt is
automatically processed.
■ Operation flow of the Extended Intelligent I/O Service (EI
Figure 7.6-7 shows the flow of EI
Figure 7.6-7 Flow of Extended Intelligent I/O Service (EI
ISD:
ISCS:
IF:
BW:
BF:
DIR:
SE:
2
OS operation based on the internal microcode of the CPU.
Interrupt request generated
by peripheral function
ISE = 1
YES
Read ISD/ISCS
Termination
request from peripheral
function
NO
DIR = 1
NO
Data indicated by IOA
(data transfer)
memory indicated by BAP
YES
IF = 0
NO
BF = 0
NO
Decrement DCT
DCT = 00
NO
Set S1 and S0 to 00
Clear interrupt request from
the peripheral function
Return to CPU operation
EI²OS descriptor
EI²OS status register
IOA update/fixed selection bit inte EI²OS status register (ISCS)
Transfer data length specification bit in the EI²OS status register (ISCS)
BAP update/fixed selection bit in the EI²OS status register (ISCS)
Data transfer direction specification bit in the EI²OS status register (ISCS)
EI²OS termination control bit in the EI²OS status register (ISCS)
NO
Interrupt sequence
YES
SE = 1
YES
Data indicated by BAP
(data transfer)
memory indicated by IOA
Updage value
Update IOA
by BW
YES
Updage value
by BW
Update BAP
(-1)
2
EI
OS termination processing
YES
Set S1 and S0 to 01
Clear ISE to 0
Interrupt sequence
DCT:
IOA:
BAP:
ISE:
S1, S0: EI²OS status in the interrupt control
CHAPTER 7 INTERRUPT
2
OS activation is set in
2
OS to transfer
2
OS)
2
OS) Operation
YES
NO
Set S1 and S0 to 11
Data counter
I/O register address pointer
Buffer address pointer
EI²OS enable bit in the interrupt control
register
register (ICR)
2
OS)
145
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