Interrupt Of Extended Intelligent I/O Service (Ei 2 Os) - Fujitsu MB90460 Series Hardware Manual

F2mc-16lx 16-bit microcontroller
Table of Contents

Advertisement

7.6
Interrupt of Extended Intelligent I/O Service (EI
The extended intelligent I/O service (EI
peripheral function (I/O) and memory. When the data transfer terminates, a hardware
interrupt is generated.
■ Extended Intelligent I/O Service (EI
The extended intelligent I/O service is a type of hardware interrupt. It automatically transfers data between
a peripheral function (I/O) and a memory. Traditionally, data transfer with a peripheral function (I/O) has
been performed by the interrupt processing program. EI
direct memory access (DMA). At termination, EI
branches to the interrupt processing routine. The user creates programs only for EI
termination. Data transfer programs in between are not required.
Advantages of extended intelligent I/O service (EI
Compared to data transfer performed by the interrupt processing routine, EI
advantages.
• Coding a transfer program is not necessary, reducing program size.
• Because transfer can be stopped depending on the peripheral function (I/O) status, unnecessary data
transfer can be eliminated.
• Incrementing or no update can be selected for the buffer address.
• Incrementing or no update can be selected for the I/O register address.
Extended intelligent I/O service (EI
When data transfer by EI
control register (ICR). Processing then automatically branches to the interrupt processing routine.
2
The EI
OS termination factor can be determined by checking the EI
interrupt processing program.
Interrupt numbers and interrupt vectors are permanently set for each peripheral. See "7.2 Interrupt Causes
and Interrupt Vectors", in Chapter 7 for more information.
Interrupt control register (ICR)
This register, which is located in the interrupt controller, activates EI
displays the EI
Extended intelligent I/O service (EI
This descriptor, which is located in RAM at 000100
transfer mode, I/O address, transfer count, and buffer address. The descriptor handles 16 channels. The
channel is specified by the interrupt control register (ICR).
2
OS) automatically transfers data between a
2
OS)
2
OS) termination interrupt
2
OS terminates, a termination condition is set in the S1 and S0 bits in the interrupt
2
OS termination status.
2
OS) descriptor (ISD)
2
OS performs this data transfer in the same way as
2
OS sets the termination condition and automatically
2
OS)
2
OS status (ICR: S1, S0) with the
2
OS, specifies the EI
to 00017F
, is an eight-byte data that retains the
H
H
CHAPTER 7 INTERRUPT
2
OS)
2
OS activation and
2
OS has the following
2
OS channel, and
139

Advertisement

Table of Contents
loading

This manual is also suitable for:

Mb90465 series

Table of Contents