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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.1
Overview of the 512K / 1024K Bit Flash Memory
The 512K bit flash memory is allocated in the FF bank on the CPU memory map while
1024K bit flash memory is allocated in FE and FF bank. The function of the flash
memory interface circuit enables the read/access or program access from the CPU to
the flash memory, same as the mask ROM. The write/delete operation to the flash
memory can be executed through the flash memory interface circuit by executing an
instruction issued from the CPU. Therefore, the flash memory mounted can be
rewritten under the control of the internal CPU, so that the program or data can be
upgraded or updated more efficiently. However, no selector operation such as the
enable sector protect can be used.
■ Characteristics of the 512K / 1024K Bit Flash Memory
• 512K Bit: 64K words x 8 bits/32K words x 16 bits
(16K+8K+8K+32K) sector configuration
• 1024K Bit: 128K words x 8 bits/64K words x 16 bits
(64K+16K+8K+8K+32K) sector configuration
• Automatic program algorithm (same as the Embedded Algorithm
: MBM29F400TA)
• Installation of the deletion temporary stop/delete restart function
• Write/delete completion detected by the data polling or toggle bit
• Write/delete completion detected by the CPU interrupt
• Compatibility with the JEDEC standard-type command
• Each sector deletion can be executed (Sectors can be freely combined)
• Number of write/delete operations 10,000 times guaranteed
*: Embedded Algorithm
■ Procedure for Writing/Deleting the data to the Flash Memory
The write/delete operation of the flash memory cannot be executed simultaneously. In executing the data
write/delete operation in the flash memory, only the write operation can be executed without a program
access from the flash memory, by copying a program on the flash memory to RAM and executing the
program.
■ Register on the Flash Memory
• Flash memory control status register (FMCS)
bit
Address:0000AE
H
Read/Write
Initial value
588
TM
is the trademark of Advanced Micro Devices, Inc.
7
6
WE
INTE
RDYINT
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
5
4
3
RDY
Reserved
(R)
(W)
(1)
(0)
TM *
2
1
LPM1
Reserved
(W)
(W)
(0)
(0)
0
LPM0
(R/W)
(0)
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