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18.5
Operation of the DTP/External Interrupt Circuit
The DTP/external interrupt circuit provides the external interrupt function and the DTP
function. This section describes the settings required for each function and the
operation of the circuit.
■ Setting the DTP/external Interrupt Circuit
Figure 18.5-1 shows the settings required to operate the DTP/external interrupt circuit.
bit
15
ICR08/ICR07
or
ICS3 ICS2 ICS1 ICS0 ISE
ICR05/ICR04
EIRR/
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
ENIR
ELVR
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4
DDR1
DDR6
:
Used
:
Set the bit corresponding to the bit used to 1
:
Set the bit corresponding to the bit used to 0
:
0
Specifies 0
1
:
Specifies 1
Set the DTP/external interrupt circuit registers with the following procedure:
1. Set as an input port the general I/O port to be used also as a pin to input external interrupts.
2. Set the target bit of the DTP/interrupt enable register (ENIR) to disable interrupts.
3. Set the target bit of the request level setting register (ELVR).
4. Clear the target bit of the DTP/interrupt cause register (EIRR).
5. Set the target bit of the DTP/interrupt enable register (ENIR) to enable interrupts.
The procedure for setting the DTP/external interrupt circuit registers must start with disabling the output of
external interrupt requests (ENIR:EN7 to EN0 = 0). Before the output of external interrupt requests can be
enabled (ENIR:EN7 to EN0 = 1), the corresponding interrupt request flag bits must be cleared (ENIR:EN7
to EN0 = 0).
This is in order to avoid interrupt requests from being generated accidentally while the registers are being
set.
Figure 18.5-1 DTP/external Interrupt Circuit
14
13
12
11
10
9
IL2
IL1
P16 P15 P14 P13 P12 P11 P10
P63
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
8
7
6
5
4
3
IL0
ICS3 ICS2 ICS1 ICS0 ISE
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
2
1
0
IL2
IL1
IL0
For the external interrupt function
For the DTP function
525
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