Fujitsu MB90460 Series Hardware Manual page 213

CHAPTER 9 I/O PORT
■ Block Diagram of Port 5 Pins
Figure 9.8-1 is a block diagram of port 5 pins.
Port data direction register (DDR)
For a pin used as an input port, reset the corresponding DDR5 register bit to "0", and also reset the
corresponding ADER register bit to "0".
For an pin used as an analog input pin, reset the corresponding DDR5 register bit to "0" and set the
corresponding ADER register bit to "1". In this case, the value read from the PDR5 register is "0".
■ Port 5 Registers
Port 5 registers are PDR5, DDR5 and ADER. The bits making up each register correspond to the port 5
pins on a one-to-one basis. Table 9.8-2 lists the port 5 pins and their corresponding register bits.
Table 9.8-2 Port 5 Pins and their Corresponding Register Bits
Port
PDR5, DDR5, ADER
Port 5
Corresponding pin
194
Figure 9.8-1 Block Diagram of Port 5 Pins
ADER
Port data register (PDR)
PDR read
Output latch
PDR write
Direction latch
DDR write
DDR read
Register bits and corresponding port pins
bit15
P57
Standby control (SPL = 1)
bit14 bit13 bit12
P56 P55 P54
Analog input
bit11 bit10
P53 P52
Pin
bit9 bit8
P51 P50