Fujitsu MB90460 Series Hardware Manual page 536

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DTP/external interrupt input detection circuit
Upon detecting the level or edge selected for each pin by the interrupt request level setting register
(ELVR), this circuit sets to "1" the IR bit of the DTP/external interrupt cause register (EIRR) that
corresponds to the pin.
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Request level setting register (ELVR)
This register selects the effective level or edge for each pin.
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DTP/interrupt cause register (EIRR)
This register stores DTP/external interrupt causes. It contains an external interrupt request flag bit for each
pin. The bit is set to "1" if a valid signal is input to the corresponding pin.
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DTP/interrupt enable register (ENIR)
This register enables and disables external interrupts for each pin.
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
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