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CHAPTER 15 MULTI-PULSE GENERATOR
●
Timer Buffer Register (TMBR)
The Timer Buffer Register (TMBR) is used store the value of the 16-bit Up Counter when a write timing
interrupt or position detect interrupt occurs.
●
Timer Control Register (TCSR)
The Timer Control Status Register (TCSR) is used to control the operation of the 16-bit timer such as the
clock frequency, enable/disable the interrupt.
■ Block Diagram of Data Write Control Unit
Write OPDBR0
From 16-bit
reload timer 0
TOUT
To 16-bit
reload timer 0
TIN
From position
detect circuit
WTIN1
●
1-Cycle Delay Circuit
The 1-Cycle Delay Circuit is used to delay one CPU clock cycle of the trigger signal when the Output Data
Buffer Register 0 (OPDBR0) is written.
364
Figure 15.2-4 Block Diagram of Data Write Control Unit
1-CYCLE
DELAY
CIRCUIT
FALLING
EDGE
WTIN0
DETECTOR
RISING AND
FALLING
EDGE
DETECTOR
TIN0O
SELECTOR 0
WTIN1
DECODER
OPS2
OPS1
OPS0
SELECTOR 1
WTO
Pin
P15/INT5/TIN0
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