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CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
18.4.2
DTP/interrupt Enable Register (ENIR)
The DTP/interrupt enable register (ENIR) enables and disables the output of interrupt
requests to the CPU.
■ DTP/interrupt Enable Register (ENIR)
bit
Address
000030
H
R/W
: Read/write enabled
Initial value
:
Table 18.4-2 Function Description of Each Bit of the DTP/interrupt Enable Register (ENIR)
Bit name
bit7
EN7 to EN0:
to
External interrupt
bit0
request enable bits
Note:
Immediately before enabling the DTP/external interrupt (ENIR:EN=1), clear the corresponding DTP/
external interrupt request flag bit (EIRR:ER).
522
Figure 18.4-3 DTP/interrupt Enable Register (ENIR)
15
8
7
(EIRR)
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
R/W R/W R/W R/W
Each of these bits enables and disables the output of interrupt requests to the CPU. If
these bits and corresponding bits ER7 to ER0 of the DTP/interrupt cause register
(EIRR) are "1", an interrupt request is output to the CPU.
(References)
• To use a DTP/external interrupt pin, write "0" to the corresponding bit of the
port direction register to set the pin as an input port.
• The states of the DTP/external interrupt pins can be read directly using the port
data register regardless of the states of external interrupt request enable bits.
• Bits ER7 to ER0 of the DTP/interrupt cause register (EIRR) are set to "1" if an
interrupt cause is detected regardless of the values of external interrupt request
enable bits.
6
5
4
3
2
R/W R/W R/W R/W
EN7
External interrupt request enable bits
EN0
0
An external interrupt request is disabled.
1
An external interrupt request is enabled.
Function
1
0
Initial value
00000000
B
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