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CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ 16-bit Output Compare Timing
When the free-run timer matches the value set in the compare register, the output compare unit generates a
compare match signal to invert the output and generate an interrupt. When a compare match occurs, the
output is inverted in synchronization with the count timing of the counter.
Note:
When the compare register is updated, comparison with the counter value is not performed.
Figure 14.6-17 Compare Operation upon Update of Compare Registers
Counter value
Compare
register 0 value
Compare
register 0 write
Compare
register 1 value
Compare
register 1 write
φ
Counter value
Compare
register
value
Compare
match
Interrupt
Counter value
Compare
register
value
Compare
match
signal
Pin output
336
N
M
L
Compare 0 stop
Figure 14.6-18 Compare Interrupt Timing
N
Figure 14.6-19 Output Pin Change Timing
N
N+1
N+1
N+2
No match signal is generated.
N+1
N
N
N
N+3
N+3
Compare 1 stop
N+1
N+1
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