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Table 15.4-9 Timer Control Status Register (TCSR)
Bit name
TCLR:
bit7
Timer clear bit
MODE:
bit6
Timer reset
condition bit
ICLR:
Compare clear
bit5
interrupt request
flag bit
ICRE:
Compare clear
bit4
interrupt request
enable bit
TMEN:
bit3
Timer enable bit
bit2
CLK2 to CLK0:
to
Clock frequency
bit0
selection bit
• The read value is always "0".
• Writing "1" to this bit initialize the counter to "0000
• Writing "0" has no effect.
• This bit is used to set the reset condition for the 16-bit timer.
• When it is "0", 16-bit timer is reset by the write timing signal.
• When it is "1", 16-bit timer is reset by the position detection signal.
(Note)
Reset of the counter value is done at the changing point of the count value.
• This bit is an interrupt request flag for compare clear.
• When the compare clear register and 16-bit free-run timer value are matched, the
counter is cleared and this bit becomes "1".
• Interrupt is generated when the interrupt request enable bit (bit12: ICRE) is set to
"1".
• Writing "0" clears this bit.
• Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
• This is the interrupt request enable bit for the compare clear.
• When this bit is "1" and the interrupt flag (bit13: ICLR) is set to "1", an interrupt
is generated.
• This bit is used to enable/disable the counting of the 16-bit timer.
• Writing "1" to this bit enables the counting of the 16-bit timer.
• Writing "0" to this bit disables the counting of the 16-bit timer.
(Note)
When the 16-bit timer is disable, the output compare operation is also disabled.
• These bits are used to select count clock for the 16-bit free-run timer.
(Note)
It is recommend to change these bits when the timer is in stop state because the
clock is changed as soon as these bits are updated.
CHAPTER 15 MULTI-PULSE GENERATOR
Function
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