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■ Clock Mode
●
PLL clock mode
A PLL clock that is a multiple of the oscillation clock (HCLK) frequency is used to operate the CPU and
peripheral functions.
●
Main clock mode
The main clock, with a frequency one-half that of the oscillation clock (HCLK), is used to operate the CPU
and peripheral functions. In main clock mode, the PLL multiplier circuit is inactive.
Reference:
See "5.1 Clock", for details about clock mode.
■ CPU Intermittent Operation Mode
CPU intermittent operation mode causes the CPU to operate intermittently, while high-speed clock pulses
are supplied to peripheral functions, reducing power consumption. In CPU intermittent operation mode,
intermittent clock pulses are only applied to the CPU when it is accessing a register, internal memory, a
peripheral function, or an external unit.
■ Standby Mode
In standby mode, the low power consumption control circuit stops supplying the clock to the CPU (sleep
mode) or the CPU and peripheral functions (time-base timer mode), or stops the oscillation clock itself
(stop mode), reducing power consumption.
●
PLL sleep mode
PLL sleep mode is activated to stop the CPU operating clock when the microcontroller enters PLL clock
mode; other components continue to operate on the PLL clock.
●
Main sleep mode
Main sleep mode is activated to stop the CPU operating clock when the microcontroller enters main clock
mode; other components continue to operate on the main clock.
●
PLL time-base timer mode
PLL time-base timer mode causes microcontroller operation, with the exception of the oscillation clock,
PLL clock and time-base timer, to stop. All functions other than the time-base timer are deactivated.
●
Main time-base timer mode
Main time-base timer mode causes microcontroller operation, with the exception of the oscillation clock,
main clock and the time-base timer, to stop. All functions other than the time-base timer are deactivated.
●
Stop mode
Stop mode causes the source oscillation to stop. All functions are deactivated.
Note:
Because stop mode turns the oscillation clock off, this mode saves most power while data is being
retained.
If the mode is switched to another clock mode or low-power-consumption mode before completion of
switching, the mode may not be switched.
CHAPTER 6 LOW POWER CONSUMPTION MODE
91
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