Timer Control Status Register (Tccsh, Tccsl) - Fujitsu MB90460 Series Hardware Manual

14.4.3

Timer Control Status Register (TCCSH, TCCSL)

The timer control status register (TCCS) is a 16-bit register and used to control the
operation of 16-bit free-run timer.
■ Timer Control Status Register, Upper Byte (TCCSH)
Address bit15 14
00005F ECKE IRQZFIRQZE MSI2 MSI1 MSI0 ICLR ICRE 00000000
H
R/W R/W
R/W : Read and Write
: Initial value
Figure 14.4-8 Timer Control Status Register (TCCSH)
13 12 11 10
R/W R/W R/W R/W
CHAPTER 14 MULTI-FUNCTIONAL TIMER
9 8 Initial value
R/W R/W
ICRE Compare clear interrupt request enable bit
0 Disable interrupt request
1 Enable interrupt request
Compare clear interrupt flag bit
ICLR
Read
0 No compare-clear match
1 Compare-clear match
MSI2 MSI1 MSI0 Interrupt masking selection bits
0 0 0 Interrupt is generated when 1st match
0 0 1 Interrupt is generated when 2nd match
0 1 0 Interrupt is generated when 3rd match
0 1 1 Interrupt is generated when 4th match
1 0 0 Interrupt is generated when 5th match
1 0 1 Interrupt is generated when 6th match
1 1 0 Interrupt is generated when 7th match
1 1 1 Interrupt is generated when 8th match
IRQZE Zero detect interrupt request enable bit
0 Disable interrupt request
1 Enable interrupt request
Zero detect interrupt flag bit
IRQZF
Read
0 No zero detect
1 Zero detect
ECKE Clock selection bit
0
1
B
Write
Clear this bit
No effect
Write
Clear this bit
No effect
Internal clock
External clock
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