Fujitsu MB90460 Series Hardware Manual page 280

CHAPTER 13 16-BIT PPG TIMER
Figure 13.3-2 Block Diagram of the 16-bit PPG Timer 2 Pin
Resource output Resource input
Resource output enable
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
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