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Port operation after a reset
• When the CPU is reset, the DDR1 and RDR registers are initialized to "0". As a result, the output buffer
is turned off (I/O mode changes to input), the pull-up resistor is cut, and the pins are placed in a high
impedance state.
• The PDR1 register is not initialized when the CPU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR1 register after the output data is set in the PDR1 register.
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Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a high-
impedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR1 register. Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit.
Note also that when a pull-up resistor is selected, the port pins are held at the high level and not placed in a
high-impedance state even when the SPL bit is set to "1". Table 9.4-4 lists the states of the port 1 pins.
Table 9.4-4 States of Port 1 Pins
Pin
Normal operation
P10/INT0/
General-purpose
DTTI0 to P17/
I/O port
FRCK
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z : High impedance
*
: Only when P10/INT0 to P16/INT6 is configured as external interrupt pins, otherwise input shutdown
Stop mode or time-base
Sleep mode
timer mode
(SPL = 0)
General-purpose
General-purpose I/O port
I/O port
CHAPTER 9 I/O PORT
Stop mode or time-base
Stop mode or time-base
timer mode
(SPL = 1, RDR = 0)
Input enabled*/output in
Input shut down/held at H
Hi-Z
level
timer mode
(SPL = 1, RDR = 1)
177
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