A/D Data Register (Adcr0/Adcr1) - Fujitsu MB90460 Series Hardware Manual

CHAPTER 20 8/10-BIT A/D CONVERTER
20.4.3

A/D Data Register (ADCR0/ADCR1)

The A/D data register (ADCR0/ADCR1) holds the result of A/D conversion and selects
the resolution of A/D conversion.
■ A/D Data Register (ADCR0/ADCR1)
bit 15 14
000037
S10 ST1
H
000036
H
R/W W
554
Figure 20.4-4 A/D Data Register (ADCR0/ADCR1)
13 12 11 10 9
-
ST0 CT1 CT0 D9
W W W - R
8 7 6 5 4
D8 D7 D6 D5 D4
R R R R R
D9 to D0
Conversion data
CT1 CT0
0 0
44 machine cycles (5.50µs@8MHz)
0 1
66 machine cycles (4.12µs@16MHz)
1 0
88 machine cycles (5.50µs@16MHz)
1 1
176 machine cycles (11.0µs@16MHz)
ST1 ST0 Sampling time setting bits
0 0 20 machine cycles (2.5µs@8MHz)
0 1 32 machine cycles (2.0µs@16MHz)
1 0 48 machine cycles (3.0µs@16MHz)
1 1 128 machine cycles (8.0µs@16MHz)
S10
0 10-bit resolution mode (D9 to D0)
1 8-bit resolution mode (D7 to D0)
3 2 1 0
Initial value
D3 D2 D1 D0
00000
R R R R
XXXXXXXX
AD data bits
Comparison time setting bits
AD data bit
-XX
B