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CHAPTER 9 I/O PORT
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Port operation after a reset
• When the CPU is reset, the DDR4 register is initialized to "0". As a result, the output buffer is turned
off (I/O mode changes to input), and the pins are placed in a high impedance state.
• The PDR4 register is not initialized when the CPU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR4 register after the output data is set in the PDR4 register.
●
Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a high-
impedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR4 register. Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit.
Table 9.7-4 lists the states of the port 4 pins.
Table 9.7-4 States of Port 4 Pins
Pin
Normal operation
P40/SIN0 to
General-purpose I/O
P46/PPG2
port
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z: High impedance
192
Stop mode or time-base
Sleep mode
timer mode (SPL = 0)
General-purpose I/O
General-purpose I/O port
port
Stop mode or time-base
timer mode (SPL = 1)
Input shut down/output in
Hi-Z
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