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1.3
Block Diagram of MB90460/465 Series
Figure 1.3-1 shows a overall block diagram of the MB90460/465 series.
■ MB90460/465 Series Block Diagram
X0
X1
RSTX
P11/INT1
P13/INT3 to
2
P14/INT4
P40/SIN0
P41/SOT0
P42/SCK0
1
P36/PPG1*
P16/INT6/TO0
P15/INT5/TIN0
1
P43/SNI0*
to
3
1
P45/SNI2*
1
P00/OPT0*
1
P01/OPT1*
1
P02/OPT2*
1
P03/OPT3*
1
P04/OPT4*
1
P05/OPT5*
P12/INT2/
1
P06/PWI0*
1
P07/PWO0*
P46/PPG2
Note: P00 to P07 (8 channels): With registers that can be used as input pull-up resistors
P10 to P17 (8 channels): With registers that can be used as input pull-up resistors
1
*
: Resource function for these pins are not applicable to MB90465 series
2
*
: Not present in MB90465 series
Figure 1.3-1 MB90460/465 Series Overall Block Diagram
Clock control
circuit
F
Reset circuit
(Watchdog timer)
Interrupt controller
8
DTP/External interrupt
UART
(Ch.0)
Multi-pulse generator
2
16-bit PPG*
(Ch.1)
16-bit reload timer
(Ch.0)
3
2
Waveform*
sequencer
2
PWC*
(Ch.0)
16-bit PPG
(Ch.2)
CMOS I/O port 0, 1, 3, 4
RAM
ROM
ROM correction
ROM mirroring
CPU
2
MC-16LX family core
Time-base timer
Delayed interrupt generator
Multi-functional timer
16-bit PPG
(Ch.0)
16-bit input capture
(Ch.0 to Ch.3)
16-bit free-run
timer
16-bit output
compare
(Ch.0 to Ch.5)
Waveform
generator
16-bit reload timer
(Ch.1)
UART
(Ch.1)
CMOS I/O port 1, 2, 3, 6
CMOS I/O port 5
A/D converter
(8/10 bit)
CHAPTER 1 OVERVIEW
Other pins
Vss x 2, Vcc x 1, MD0-2, C
P37/PPG0
4
4
P24/IN0 to
P27/IN3
P17/FRCK
P30/RTO0 (U)
P31/RTO1 (X)
P32/RTO2 (V)
P33/RTO3 (Y)
P34/RTO4 (W)
P35/RTO5 (Z)
P10/INT0/DTTI0
P20/TIN1
P21/TO1
P22/PWI1
PWC
(Ch.1)
P23/PWO1
P60/SIN1
P61/SOT1
P62/SCK1
P63/INT7
P50/AN0
P51/AN1
P52/AN2
P53/AN3
8
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AV
AVR
AV
CC
SS
7
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